Semiconductor devices, such as, for example, complementary metal-oxide semiconductor (CMOS) devices are continuously being scaled down to smaller dimensions. As components are scaled down and transistors are being formed closer together, dielectrics, such as gate spacers, formed between conducting elements can cause charge build up and crosstalk, which can adversely affect device performance. Low-k dielectric materials have a small dielectric constant relative to that of silicon dioxide. Low-k dielectrics having the same thickness as dielectrics with dielectric constants greater than or equal to that of silicon dioxide can reduce parasitic capacitance and provide low contact resistance, resulting in improved device performance at smaller scales.
Due to conventional methods for forming field-effect transistors (FETs), spacer material must be able to withstand aggressive epitaxial pre-cleaning processes, etching processes, and high temperature processes, such as epitaxial growth. As a result, the universe of available low-k dielectrics that can tolerate current processing flows is limited.